1. Field of the Invention
This invention relates to electronic circuitry and in particular to printed circuit board technology.
2. Art Background
The electrical interconnection between printed circuit boards in electronic equipment contributes significantly to the price of the equipment. Thus, there has been widespread effort to increase the interconnection density of printed circuit boards and thus decrease their size and associated cost. In one configuration employed to increase interconnection density, printed circuit patterns are placed on both major surfaces of a substrate such as a glass reinforced epoxy substrate. Electrical interconnections between points in the two patterns are made by drilling through the substrate and metallizing the hole. This configuration significantly increases the capacity of one printed circuit board. However, the holes drilled for interconnection are large, e.g., approximately 0.015 to 0.045 inches. Since the holes are larger than the typical width of a pattern section, generally 0.005 to 0.015 inches, they extend beyond the limits of a pattern line. Adjacent pattern lines must be deflected to avoid short circuits with the enlarged metallized portion surrounding the interconnection hole. Thus, the holes occupy a significant area and therefore increase the size of the printed circuit. In addition, these holes necessitate an increased complexity in the design of the printed circuit board pattern.
Multiple level pattern configurations have also been employed to further increase the capacity of printed circuit boards. In one such configuration, printed circuit board patterns, 9, are formed on both major surfaces of two or more separate substrates (C-stages, 5, in FIG. 1). An adhesive bonding layer, for example, an epoxy impregnated glass cloth, (B-stage, 7, in FIG. 1), is sandwiched between two or more substrates each having their associated copper patterns on both major surfaces. The multilevel configuration is completed by sandwiching the two C-stages and the intermediate B-stage between external layers which include a copper foil, 4, and an additional C-stage layer, 8 with their associated B-stage, 10. The entire structure is pressed together at an elevated temperature. The pressure and elevated temperature cures the B-stage resin and produces a monolithic structure. By appropriately configuring the copper patterns on the outer copper foil layer and by appropriately aligning the resin-encapsulated inner pattern on each substrate, electrical interconnection between the patterns on different substrates is possible by drilling holes completely through the structure and metallizing the holes. However, there are significant difficulties associated with aligning the appropriate sections of the patterns on each substrate so that a suitable electrical interconnection is made. Additionally, in this multiple level configuration, electrical contact between patterns on the same substrate are made as described previously in the two-sided printed circuit board. Thus, the problems encountered with two-sided printed circuit boards, e.g., large holes producing increased size and pattern complexity are also inherent in this multiple level board. Further, since an interconnection hole is drilled through the entire structure an interconnection between two patterns induces a hole with its associated complications in all the circuit layers.
A multiple level circuit board has been developed that does not require the physical alignment of two independent substrates. In this process, as shown in FIG. 2, a copper layer, 12, is deposited on a stainless steel carrier, 14. A photoresist is applied to the copper layer and imaged in the desired pattern so that the copper areas of the underlying layer forming the desired pattern are covered and the remainder of the copper layer is exposed. The exposed copper is removed by etching and the photoresist is then removed leading to configuration 2B. A new photoresist layer is deposited and delineated so that holes, 17, in the resist, 13, are opened where connections between pattern levels are to be made. Copper is then evaporated onto the substrate over the resist and thus as a consequence, onto the exposed regions of the copper pattern leading to configuration, 2D. The photoresist is removed to leave the pattern, 18, with interconnection studs, 19 in configuration 2E. Polyimide resin is deposited onto the copper to yield configuration, 2F. The top of the polyimide is abraded to expose the copper structures, 19 in 2G. A photoresist is deposited onto the polyimide and suitably delineated to leave exposed areas of the polyimide where the second level copper pattern is to be formed leading to 2H. (This pattern includes the copper studs which are used as interconnection between the pattern levels.) A second copper layer is then deposited on the exposed polyimide and copper studs and the photoresist is removed leading to configuration 2I. The steps are repeated to produce successive patterned layers. That is, photolithography is again done by conventional techniques to delineate the desired interconnection openings, copper is evaporated onto the resist, the resist is removed, a second layer of polyimide is deposited, the surface of the polyimide is abraded to expose the copper, photolithography is employed to delineate the next pattern layer and copper is deposited onto the resist. As can be seen from FIG. 2 and the accompanying description, a large number of processing steps are involved. Thus, a high-density printed circuit board that is producible in a nominal number of steps is not yet available.